Hardware IP

The WSP Processor targeted for PON gateways and wireless routers guarantees wire speed secure routing of any size packets between Gigabit Ethernet ports. The architecture is highly scalable for multiple Ethernet ports, higher data rates and peripherals with other protocols like ATM. At the heart of the WSP is a C-Programmable classification engine for packet classification based on standard protocols. The architecture has hardware engines for compute intensive QoS, Multicast etc. Posedge delivers RTL IP and software stack running on Host to realize a complete SoC.

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PSS is a highly configurable AMBA AXI/AHB based SoC Platform with flexible number of masters/slaves, bus sizes, frequencies, arbitration. The bus structures can be configured for higher throughput or lower area by distributing master muxes and slave muxes. The platform includes highly configurable DDR I/II controller with support for rates up to 533 MHz, Gigabit Ethernet Controller with supports GMII/RGMII interfaces, Serial Peripheral Controller, I2C Master Slave Controller, AHB 2.0 Compliant 4 Channel General Purpose DMA, AHB 2.0 Master/Slave/Arbiter, UART, General Purpose Timer and GPIO. The platform is delivered with reference C-drivers.

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Posedge-L2SEC – High-Performance IEEE 802.1AE (MACSec) Processing Engine

Posedge-L2SEC implements the complete MACsec data plane functionality. It performs functions such as AES-GCM, Classification & Filtering, SecTAG processing, Anti-Replay check, ICV verification, and MIB Statistics. The engine can process the MAC frames up to 10Gbps full-duplex throughput for all packet sizes.  It is highly configurable and easy to  integrate.

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Posedge Universal Security (UNISec) Engine

Posedge Universal Security Engine is a multiple protocol processing engine. The IP core can support eight 1Gbps ports or one 10Gbps port. The architecture handles different security protocols like   MACSec, IPSec and DTLS. It addresses the universal issue of IT Security by providing information   security and integrity against the rise of security breaches with increased data traffic. The Posedge UNISec Engine architecture comprises of a packet Mux, packet processor, packet De-Mux, CPU inteface and SAD inteface.

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Posedge Universal Flash Controller (UFC)

Posedge Universal Flash Controller (UFC) is a flexible high performance Soft IP core capable to  interface with NAND, NOR and Serial Flash devices conforming to the latest Open NAND Flash Interface Working Group standards. It has a very generic and modular architecture with AXI/AHB/APB/FIFO interfaces to meet various customer specific requirements. The UFC core internally AHB/APB slave interface to connect to SoC and Serial peripheral, NAND, NOR industry standard interfaces towards the Flash memory. The data transfer between external flash or serial devices and the flash controller is through the register I/O. The UFC core supports NAND flash access at up to 200 MTps (Million transfers per second) with transfer size of 8bits or 16 bits depending upon the mode and Serial flash accesses up to 70 Mbps enabling faster data access and boot times. To avoid data throttling at the host processor side the IP core has an internal 16 deep Data Buffer which can queue up to 16 commands. The architecture ensures to easily meet timing at all the interfaces.

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The Posedge Universal SD/SDIO/MMC Host Controller Core is highly configurable and is compatible with standard SD Host 3.0 and eMMC4.4 specification. The Host Controller Core supports three key interfaces namely SD, SDIO, and eMMC. The Core supports Programmed IO mode (PIO), Simple DMA (SDMA), and powerful scatter/ gather DMA (ADMA) for data transfer. Using the Posedge Universal SD/SDIO/MMC Host Controller Core, the Host driver can access memory up to 2TB. The Core is designed to operate at a maximum operating frequency of 208MHz to achieve maximum throughput of 832Mbits/sec.

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Posedge USB-SATA Offload Engine (USOE) offloads bulk traffic between the USB Device and SATA Host. The USB-SATA adapters are ubiquitous in SSD drives, backup retrieval systems, and commodity disk drivers. However the performance of the data transfer is very limited because of the number of functions that need to be performed by the software. Current systems have the USB, SATA protocol conversion, segmentation and reassembly of the packets, and STATUS packet generation etc. at the Software driver level. Posedge USOE offloads the performance hindering common software tasks from the local host and implements them in hardware. The USOE works as a proxy for both the USB and SATA devices for the local host. All the accesses from the local host are interpreted, translated and presented to the USB Device and SATA Host. In transparent mode, the accesses from the local host are directly sent to the peripherals. Posedge USOE works with buffers on the AXI/AHB bus and hence the temporary store can be on-chip memory or off-chip DDR. The AXI/AHB master interface of the off-load engine accesses data from the peripherals and interprets it. In certain cases, the engine creates packets and schedules the DMA (Status Packet).

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Posedge PZLIB engine implements standard DEFLATE algorithm compliant with RFC1951. Deflate algorithm is a lossless data compression algorithm that uses a combination of LZ77 (patent free) algorithm and Huffman Coding. Deflate is widely used in common compression programs like ZLIB, GZIP. A deflate stream consists of a series of blocks and each block can be coded differently depending on the trade-off between the level of compression and the complexity of the computation. Posedge PZLIB is compliant with IPCOMP protocol as per the RFC2393 used for compression of TCP/IP traffic for efficient use of bandwidth. PZLIB implements deflate with options to have limited back tracking, optional compression in a stream (based on packet size and compression ratio), and IPCOMP Header formation to suite IP Compression. In addition, the low power features enable the usage of PZLIB in mobile applications.

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Posedge-SSL is a complete SSL VPN protocol processor. The IP has posedge-TOE engine for complete TCP processing and session termination. posedge-SSL IP is highly flexible with a programmable controller for encapsulation and the crypto engines are implemented in hardware.

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Posedge-IPSEC-1.0 is a complete IPSEC protocol processor for IPV4 and IPV6. The IP is highly flexible with a programmable controller for ESP/AH encapsulation and the crypto engines are implemented in hardware. The engine is very powerful and can process a Gigabit of short IP data.

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Posedge Datagram Transport Layer Security (DTLS) is defined RFC4347 of the Network Working Group of the IETF. It primarily provides communications privacy for datagram protocols and allows client/server applications to communicate in a way that prevents eavesdropping, tampering, or message forgery. The DTLS protocol is based on the Transport Layer Security (TLS) protocol and provides equivalent security guarantees. DTLS preserves the datagram semantics of the underlying transport layer data and unlike TLS that needs to run over a connection oriented protocol, DTLS is suited for connectionless protocols such as UDP.

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Posedge AES Crypto Engine IP is a Silicon-proven high performance crypto core. The core is flexible and can be configured for various data rates and sizes depending on the application. The design supports EBC, CBC, and CTR modes of operation and is used in variety of applications including high end security devices implementing IPSEC.

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